1. Field of the Invention
The present invention relates to a semiconductor device, a testing method, and a programming method.
2. Description of the Related Art
Semiconductor memories are generally classified into volatile memories from which information is erased when the power source is switched off, and non-volatile memories in which information is maintained even when the power source is switched off. As a representative type among the non-volatile memories, flash memories having the rewrite time shortened by collectively erase data are known. Examples of flash memories that are not affected by variations in device characteristics are described in the following.
The device that is disclosed in Japanese Unexamined Patent Publication No. 2002-197880 determines the optimum programming conditions such as program widths in an operation test mode, and stores the information in the chip. In a regular operating mode, a control circuit accesses the information, and causes the device to operate under the programming conditions unique to the chip. The device that is disclosed in Japanese Unexamined Patent Publication No. 2003-223791 sets a voltage increase width for each chip for the time of step programming by a programming unit.
In recent years, flash memories with multilevel memory cells have been developed. FIG. 1 illustrates the threshold value distribution in multilevel memory cells. In FIG. 1, the abscissa axis indicates the threshold value, and the ordinate axis indicates the number of bits. In a device with multilevel memories, there are four memory cell levels of level 1, level 2, level 3, and level 4, and these four levels form two sets of output (or input) data. When programming is performed at level 4, a programming method by which level 4 is reached via level 1, level 2, and level 3 is generally employed.
With such multilevel memory cells, however, in a case where the threshold value Vth is in the range of 0v to 8v, the distribution of one value needs to be contained in within 1v, so as to obtain four values. So as to maintain the distribution in such a narrow region, highly precise programming operations are required. To perform highly precise programming operation, the optimum programming conditions need to be determined.
The device disclosed in Japanese Unexamined Patent Publication No. 2002-197880 determines the optimum programming conditions such as program width in an operation test mode. However, the document does not specifically disclose how the optimum programming conditions such as program widths are actually determined.
The device disclosed in Japanese Unexamined Patent Publication No. 2003-223791 sets a voltage increase width for each chip during a step programming operation. However, the document does not specifically disclose how the optimum voltage increase width is determined.